ddr: vybrid: Add calibration code to memory controler's (DDRMC) setup code

This patch extends the vf610 DDR memory controller code to support SW
leveling.

Signed-off-by: Lukasz Majewski <[email protected]>
Reviewed-by: Stefan Agner <[email protected]>

diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c
index fa948f78120c58fcb2a2f468990c4600d76520c8..461fba4d3f6ae380d7721849792b6bef500c4ff8 100644 (file)
--- a/arch/arm/mach-imx/ddrmc-vf610.c
+++ b/arch/arm/mach-imx/ddrmc-vf610.c
@@ -10,6 +10,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux-vf610.h>
 #include <asm/arch/ddrmc-vf610.h>
+#include "ddrmc-vf610-calibration.h"
 
 void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
 {
@@ -235,4 +236,8 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
        while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
                udelay(10);
        writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);
+
+#ifdef CONFIG_DDRMC_VF610_CALIBRATION
+       ddrmc_calibration(ddrmr);
+#endif
 }